8( 8google,steelix-sku131072google,steelixmediatek,mt8186 +7Google Steelix board =convertiblealiasesJ/soc/ovl@14005000O/soc/ovl@14006000W/soc/rdma@14007000]/soc/rdma@1401f000c/soc/i2c@11007000h/soc/i2c@11008000m/soc/i2c@11009000r/soc/i2c@1100f000w/soc/i2c@11016000|/soc/mmc@11230000/soc/mmc@11240000/soc/serial@11002000ccimediatek,mt8186-ccicciintermediate"opp-table-ccioperating-points-v2opp-500000000e 'opp-560000000!` Lopp-612000000$za opp-682000000(~  opp-752000000,Ҝ YF opp-8220000000  opp-8750000004'p  opp-9270000007@ 5 opp-980000000:i ~>opp-1050000000> opp-1120000000B )$opp-1155000000D opp-1190000000F opp-1260000000K~opp-1330000000OF0)opp-1400000000SrNRopp-table-cluster0operating-points-v2opp-500000000e 'opp-774000000."M Lopp-8750000004'p `opp-975000000:Q  opp-1075000000@2 q opp-1175000000F  X opp-1275000000K 5 opp-1375000000Q  opp-1500000000Yh/ opp-1618000000`p Yopp-1666000000cM$ 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21dA@cpu-retention-barm,idle-state 21dAx$cpu-off-larm,idle-state d1A4 cpu-off-barm,idle-state d1Al%l2-cache0cacheRhu@(^!l2-cache1cacheRhu@(^&l3-cachecacheRhu@^(fixed-factor-clock-13mfixed-factor-clockl)yclk13m=oscillator-26m fixed-clocklclk26m)oscillator-32k fixed-clocklclk32kopp-table-gpuoperating-points-v2sopp-299000000` Xopp-332000000 hopp-366000000з <opp-400000000ׄ Ҧopp-434000000P zopp-484000000A 4Nopp-535000000s }opp-586000000" `opp-637000000%@ 4opp-690000000)  @opp-743000000,IG opp-796000000/q opp-8500000002 5opp-900000000-35 Popp-900000000-45 |opp-900000000-55 0opp-950000000-38ـ opp-950000000-48ـ Yopp-950000000-58ـ P0opp-1000000000-3;~opp-1000000000-4; topp-1000000000-5; Y0pmu-a55arm,cortex-a55-pmu *pmu-a76arm,cortex-a76-pmu +psci arm,psci-1.0smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3      ppi-partitionsinterrupt-partition-0%*interrupt-partition-1%+syscon@c53a000mediatek,mt8186-mcusyssyscon Slsyscon@10000000 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 7, * < S@Obt-sco-codec linux,bt-sco4dmic-codec dmic-codec4 l y2gpio-keys gpio-keysdefaultpen-insert-switch Pen Insert >,   regulator-pp1800-dpbrdg-dxregulator-fixeddefault >,'pp1800_dpbrdg_dx  \Yregulator-pp3300-disp-xregulator-fixeddefault >,pp3300_disp_x   ]Nregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5) 2Z2Z regulator-pp3300-s3regulator-fixed pp3300_s3)  ]Sregulator-pp3300-z2regulator-fixed pp3300_z2) 2Z2Z ]regulator-pp4200-z2regulator-fixed pp4200_z2) @@@@ 9regulator-pp5000-z2regulator-fixed pp5000_z2) LK@LK@ regulator-ppvar-sysregulator-fixed ppvar_sys) reserved-memory+memory@61000000shared-dma-poola Cmemory@60000000shared-dma-pool` Dmemory@50000000shared-dma-poolP  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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0rdma0rdma1i2c0i2c1i2c2i2c3i2c5mmc0mmc1serial0clocksclock-namesoperating-points-v2proc-supplyphandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeregenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxinput-enablebias-pull-downinput-schmitt-enablebias-disableoutput-lowdrive-strengthoutput-highbias-pull-up#power-domain-cellsdomain-supplymediatek,infracfgmediatek,disable-extrstmediatek,reset-by-toprguinterrupts-extendedAvdd-supplymediatek,dmic-modevsys-ldo1-supplyvsys-ldo2-supplyvsys-ldo3-supplyvsys-vcore-supplyvsys-vdram1-supplyvsys-vgpu-supplyvsys-vmodem-supplyvsys-vpa-supplyvsys-vproc11-supplyvsys-vproc12-supplyvsys-vs1-supplyvsys-vs2-supplyvs1-ldo1-supplyvs2-ldo1-supplyvs2-ldo2-supplyvs2-ldo3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-coupled-withregulator-coupled-max-spreadassigned-clocksassigned-clock-parentsstatus#mbox-cellspinctrl-namespinctrl-0firmware-namememory-regionmediatek,rpmsg-namembox-namesmboxespower-domainsspi-max-frequency#io-channel-cellsenable-gpiosreset-gpiosvdd10-supplyvdd18-supplyvdd33-supplyanalogix,lane0-swinganalogix,lane1-swingremote-endpointdata-lanespower-supplybacklighti2c-scl-internal-delay-nsgoodix,no-reset-during-suspendvcc-supplywakeup-sourcehid-descr-addr#sound-dai-cellsovdd-supplypwr18-supplylink-frequenciesAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-src#pwm-cellsmediatek,pad-selectgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosmediatek,apmixedsysmediatek,topckgenresetsreset-namesphysmediatek,syscon-wakeupvbus-supplypinctrl-1bus-widthnon-removablecap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqeno-sdno-sdiocap-mmc-hw-reseths400-ds-delaymediatek,hs400-ds-dly3vmmc-supplyvqmmc-supplypinctrl-2interrupt-namescap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50keep-power-in-suspendcap-sdio-irqno-mmcmmc-pwrseq#phy-cellsmediatek,discthbitspower-domain-namesnvmem-cellsnvmem-cell-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsmediatek,scpstdout-pathpwmsbrightness-levelsnum-interpolated-stepsdefault-brightness-levelnum-channelswakeup-delay-mswakeup-event-actionlinux,codelinux,input-typeenable-active-highvin-supplyregulator-boot-onno-mappinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12pinctrl-13pinctrl-14pinctrl-15pinctrl-16pinctrl-17pinctrl-18mediatek,adspmediatek,platformsound-daisdb-gpiosgpiopost-power-on-delay-ms