RH8F( 0E.radxa,nio-12lmediatek,mt8395mediatek,mt8195 +7Radxa NIO 12L =embeddedaliasesJ/soc/dp-intf@1c015000S/soc/dp-intf@1c113000\/soc/mailbox@10320000a/soc/mailbox@10330000f/soc/hdr-engine@1c114000m/soc/mutex@1c016000t/soc/mutex@1c101000{/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000/soc/i2c@11e00000 /soc/i2c@11e01000/soc/ethernet@11021000/soc/serial@11001100!/soc/serial@11001200)/soc/spi@11010000./soc/spi@11012000cpus+cpu@03cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@1003cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@2003cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@3003cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@4003cpuarm,cortex-a78?CpsciQefu@@ cpu@5003cpuarm,cortex-a78?CpsciQefu@@cpu@6003cpuarm,cortex-a78?CpsciQefu@@cpu@7003cpuarm,cortex-a78?CpsciQefu@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state)@Q2b_rDcpu-retention-barm,idle-state)@Q-brcpu-off-larm,idle-state)@Q7brHcpu-off-barm,idle-state)@Q2brl2-cache0cache@l2-cache1cache@l3-cachecache @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-sound disabledfixed-factor-clock-13mfixed-factor-clock clk13m(oscillator-26m fixed-clocke clk26moscillator-32k fixed-clocke clk32kperformance-controller@11bc10mediatek,cpufreq-hw ? 0 opp-table-gpuoperating-points-v29oopp-390000000D>K hopp-410000000DpK opp-431000000DK opp-473000000D1h@K <opp-515000000DFK <opp-556000000D!#K Ҧopp-598000000D#K opp-640000000D&%K opp-670000000D'cK opp-700000000D)'K Lopp-730000000D+K }opp-760000000D-LK `opp-790000000D/qK 4opp-820000000D05K opp-850000000D2K @opp-880000000D4sK qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Jsmctimerarm,armv8-timer @   soc+ simple-busY`interrupt-controller@c000000 arm,gic-v3k|  ?    ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8195-topckgensyscon?syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd?syscon@10003000mediatek,mt8195-pericfgsyscon?0>pinctrl@10005000mediatek,mt8195-pinctrl?PBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintketh-default-pins:pins-ccUVWXpins-mdioYZpins-power[\pins-rst]pins-rxdQRSTpins-txdMNOPeth-sleep-pins;pins-ccUVWXpins-mdioYZ,pins-rxdQRSTpins-txdMNOPi2c2-pins]pins-bus  :Gi2c4-pins`pins-bus:Gi2c6-pinsVpinsmmc0-default-pinsBpins-clkz_fpins-cmd-dat$~}|{wvuty:epins-rstx:emmc0-uhs-pinsCpins-clkz_fpins-cmd-dat$~}|{wvuty:epins-ds_fpins-rstx:emmc1-default-pinsFpins-clko_fpins-cmd-datnpqrs:emmc1-detect-pinsGpins-insert:mt6360-pinsWpins-irqde:pcie0-default-pinsQpins-bus :pcie1-default-pinsTpins-bus spi1-default-pins4pins-busspi2-default-pins5pins-busuart0-pins/pins-busbcuart1-pins0pins-busfgwifi-vreg-pinspins-wifi-pmu-enApins-wifi-vreg-enCsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd?`power-controller!mediatek,mt8195-power-controller+n+power-domain@8?+npower-domain@9? mfgalt+npower-domain@10? npower-domain@11? npower-domain@12? npower-domain@13? npower-domain@14?npower-domain@15? @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+npower-domain@24?vdec1-0npower-domain@27? venc1-larbnpower-domain@16?8$%&'()Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+npower-domain@17?vppsys1vppsys1-0vppsys1-1npower-domain@22? $wepsys-0wepsys-1wepsys-2wepsys-3npower-domain@23? vdec0-0npower-domain@25?!vdec2-0npower-domain@26?" venc0-larbnpower-domain@18? ###&vdosys1vdosys1-0vdosys1-1vdosys1-2+npower-domain@19?npower-domain@20?npower-domain@21?Qhdmi_txnpower-domain@28?$$  img-0img-1+npower-domain@29?npower-domain@30?$%ipeipe-0ipe-1npower-domain@31?(&&&&&cam-0cam-1cam-2cam-3cam-4+npower-domain@32? npower-domain@33?!npower-domain@34?"npower-domain@0?npower-domain@1?npower-domain@2?npower-domain@3?npower-domain@4?57csi_rx_topcsi_rx_top1npower-domain@5?' ethernpower-domain@6?Xn adspadsp1+npower-domain@7? g"n2audioaudio1audio2audio3nwatchdog@10007000mediatek,mt8195-wdt?p.syscon@1000c000"mediatek,mt8195-apmixedsyssyscon?timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer?p (pwrap@10024000mediatek,mt8195-pwrapsyscon?@pwrap spiwrap$pmicmediatek,mt6359k mt6359codecregulatorsbuck_vs1vs1 5!2Nbuck_vgpu11vgpu117b2 wNbuck_vmodemvmodemb*2buck_vpuvpu7b2 wNbuck_vcorevcore b2 wNbuck_vs2vs2 5j2Nbuck_vpavpa 72,buck_vproc2vproc27bL2 wNbuck_vproc1vproc17bL2 wNbuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@2Nldo_vsim1vsim1/M`ldo_vibrvibrO2Z^ldo_vrf12vrf12 Nldo_vusbvusb--2N?ldo_vsram_proc2 vsram_proc2 bL2Nldo_vio18vio182Nldo_vcamiovcamioNldo_vcn18vcn18w@w@2ldo_vfe28vfe28**2xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@2Nldo_vsram_others vsram_others q qb2ldo_vefusevefuseldo_vxo22vxo22w@!Nldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**2ldo_vio28vio28*2ZNldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZDldo_vcn33_2_bt vcn33_2_bt2Z2Zldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O Nldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md b*2Nldo_vufsvufsEldo_vm18vm18Nldo_vbbckvbbckONldo_vsram_proc1 vsram_proc1 bL2Nldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi ?p pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+pmic@6mediatek,mt6315-regulator?regulatorsvbuck1vbuck1Vbcpu72 wNpmic@7mediatek,mt6315-regulator?regulatorsvbuck1vbuck1Vgpu72 wpinfra-iommu@10315000mediatek,mt8195-iommu-infra?1PPPNmailbox@10320000mediatek,mt8195-gce?2@mailbox@10330000mediatek,mt8195-gce?3@qscp@10500000mediatek,mt8195-scp0?Prpsramcfgl1tcmokay)clock-controller@10720000mediatek,mt8195-scp_adsp?r*dsp@10803000mediatek,mt8195-dsp ?0 cfgsram,Xn*#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h+rxtx,- disabledmailbox@10816000mediatek,mt8195-adsp-mbox?`,mailbox@10817000mediatek,mt8195-adsp-mbox?p-mt8195-afe-pcm@10890000mediatek,mt8195-audio?+6. audiosysg"#neabcd2*clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbusokay/defaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbusokay0defaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc? main( disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon?0'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+?parent-clksel-clkspi-clk disabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap? :12$Flvts-calib-data-1lvts-calib-data-2Wsvs@1100bc00mediatek,mt8195-svs?main:31(Fsvs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm?+m*0mainmm disabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm?m+Nmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+?3parent-clksel-clkspi-clkokay4defaultxspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+? 4parent-clksel-clkspi-clkokay5defaultxspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+?05parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+?<parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+?=parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave?Rspi disabledspi@1101e000mediatek,mt8195-spi-slave?Sspi disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a?@macirq.axiapbmac_mainptp_refrmii_internalmac_cg0''RST' RST+678okay rgmii-rxid9defaultsleep:;$9 J] ZN mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916?9stmmac-axi-configo6rx-queues-config7queue0queue1queue2queue3tx-queues-config8queue0queue1queue2queue3usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 ? - > macippcY ?+/Bsys_ckref_ckmcu_ck-<=2 @>gokayWhostp?usb@0'mediatek,mt8195-xhcimediatek,mtk-xhci?mac,-$/B$sys_ckref_ckmcu_ckdma_ckxhci_ckokay@portendpointAZmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc ?#sourcehclksource_cgokaydefaultstate_uhsBC L     .D :Emmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc ?$$sourcehclksource_cgokaydefaultstate_uhsFGF  G X a  h u .H :Immc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc ?% Isourcehclksource_cg  disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu?':12$Flvts-calib-data-1lvts-calib-data-2Wusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ?))> macippc-J./$''$sys_ckref_ckmcu_ckdma_ckxhci_ck @>h2okay ?Kusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 ?*-*> macippcY*?+0''sys_ckref_ckmcu_ck-L2 @>iokay?usb@0'mediatek,mt8195-xhcimediatek,mtk-xhci?mac1'sys_ckokayKusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 ?+-+> macippcY+?+2'' sys_ckref_ckmcu_ck-M2 @>j disabledusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci?mac3' sys_ck disabledpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie3pci+?/@ pcie-mac 8Y  N 0V#&+K'/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memG-O pcie-phy+mack ` PPPPokaydefaultQinterrupt-controllerkPpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie3pci+?/@ pcie-mac 8Y$$ $ $  N (WXQ'/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memH-R pcie-phy+mack ` SSSSokaydefaultTinterrupt-controllerkSspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor?29o'' spisfaxi+ disabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse?+usb3-tx-imp@184,1? fusb3-rx-imp@184,2? eusb3-intr@185? dusb3-tx-imp@186,1? cusb3-rx-imp@186,2? busb3-intr@187? ausb2-intr-p0@188,1? usb2-intr-p1@188,2? usb2-intr-p2@189,1? usb2-intr-p3@189,2? pciephy-rx-ln1@190,1? mpciephy-tx-ln1-nmos@190,2? lpciephy-tx-ln1-pmos@191,1? kpciephy-rx-ln0@191,2? jpciephy-tx-ln0-nmos@192,1? ipciephy-tx-ln0-pmos@192,2? hpciephy-glb-intr@193? gdp-data@1ac?lvts1-calib@1bc?1lvts2-calib@1d0?82svs-calib@580?d3socinfo-data1@7a0?t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Y disabledusb-phy@0?ref Lt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Y disabledusb-phy@0?ref Mdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx?  mipi_tx0_pll  disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx?  mipi_tx1_pll  disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"U; maindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"U; maindma+okayeVdefaultpmic@34mediatek,mt6360?4 eIRQBkWchargermediatek,mt6360-chg @usb-otg-vbus-regulator usb-otg-vbusC(X@regulatormediatek,mt6360-regulator X Ybuck1 emi_vdd2  wNbuck2 emi_vddq  wNYldo1 ext_lcd_3v32Z2ZwNldo2 panel1_p1v8w@w@wldo3vmc_pmuO6wIldo5 vmch_pmu2Z2ZwNHldo6 mt6360_ldo6  wldo7 emi_vmddr_en  wNtypecmediatek,mt6360-tcpc dPD_IRQBconnectorusb-c-connector +USB-C 1dual ; Mdual Xsink g"d s",ports+port@0?endpointZAport@2?endpoint[_i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ? "U; maindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s?0Ui2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"\; maindma+ disabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"\; maindma+ disabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ? "\; maindma+okaye]defaulttypec-mux@48 ite,it5205?H }  ^portendpoint_[i2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?0"\; maindma+ disabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?@"\; maindma+okaye`defaultclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w?P\t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Y+ disabledusb-phy@0?  refda_ref Jusb-phy@700? refda_ref :abcFintrrx_imptx_imp Rt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Y disabledusb-phy@0?  refda_ref <usb-phy@700? refda_ref :defFintrrx_imptx_imp =phy@11e80000mediatek,mt8195-pcie-phy?sif:ghijklmGFglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1+  disabledOufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy? unipromp  disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm?@n0 jobmmugpu o(+ + + + + core0core1core2core3core4okay pclock-controller@13fbf000mediatek,mt8195-mfgcfg?nsyscon@14000000mediatek,mt8195-vppsys0syscon? qdma-controller@14001000mediatek,mt8195-mdp3-rdma? q  + r<q q qqq display@14002000mediatek,mt8195-mdp3-fg?  q display@14003000mediatek,mt8195-mdp3-stitch?0 q0display@14004000mediatek,mt8195-mdp3-hdr?@ q@"display@14005000mediatek,mt8195-mdp3-aal?PF qP +display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?` q` % display@14007000mediatek,mt8195-mdp3-tdshp?p qp#display@14008000mediatek,mt8195-mdp3-color?I q$+display@14009000mediatek,mt8195-mdp3-ovl?J q%+ rdisplay@1400a000mediatek,mt8195-mdp3-padding? q+display@1400b000mediatek,mt8195-mdp3-tcc? qdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot? q  + r+ mutex@1400f000mediatek,mt8195-vpp-mutex?P q+smi@14010000mediatek,mt8195-smi-sub-common?apbsmigals0 s+tsmi@14011000mediatek,mt8195-smi-sub-common?apbsmigals0 s+smi@14012000mediatek,mt8195-smi-common-vpp?  apbsmigals0gals1+slarb@14013000mediatek,mt8195-smi-larb?0 % tapbsmi+wiommu@14018000mediatek,mt8195-iommu-vpp?8 6uvwxyz{|}~Rbclk+rclock-controller@14e00000mediatek,mt8195-wpesys?clock-controller@14e02000mediatek,mt8195-wpesys_vpp0? clock-controller@14e03000mediatek,mt8195-wpesys_vpp1?0larb@14e04000mediatek,mt8195-smi-larb?@ % apbsmi+larb@14e05000mediatek,mt8195-smi-larb?P % s apbsmigals+ysyscon@14f00000mediatek,mt8195-vppsys1syscon? q mutex@14f01000mediatek,mt8195-vpp-mutex?{ q '+larb@14f02000mediatek,mt8195-smi-larb?  %  apbsmigals+larb@14f03000mediatek,mt8195-smi-larb?0 % t apbsmigals+xdisplay@14f06000mediatek,mt8195-mdp3-split?` q `+,+display@14f07000mediatek,mt8195-mdp3-tcc?p q pdma-controller@14f08000mediatek,mt8195-mdp3-rdma? q   + dma-controller@14f09000mediatek,mt8195-mdp3-rdma? q    + dma-controller@14f0a000mediatek,mt8195-mdp3-rdma? q    r+ display@14f0b000mediatek,mt8195-mdp3-fg? q  display@14f0c000mediatek,mt8195-mdp3-fg? q  display@14f0d000mediatek,mt8195-mdp3-fg? q  display@14f0e000mediatek,mt8195-mdp3-hdr? q display@14f0f000mediatek,mt8195-mdp3-hdr? q display@14f10000mediatek,mt8195-mdp3-hdr? q  display@14f11000mediatek,mt8195-mdp3-aal?i q +display@14f12000mediatek,mt8195-mdp3-aal? j q +display@14f13000mediatek,mt8195-mdp3-aal?0k q 0!+display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?@ q @ display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?P q P $display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?` q ` %display@14f17000mediatek,mt8195-mdp3-tdshp?p q pdisplay@14f18000mediatek,mt8195-mdp3-tdshp? q (display@14f19000mediatek,mt8195-mdp3-tdshp? q )display@14f1a000mediatek,mt8195-mdp3-merge? q +display@14f1b000mediatek,mt8195-mdp3-merge? q +display@14f1c000mediatek,mt8195-mdp3-color?t q +display@14f1d000mediatek,mt8195-mdp3-color? q u+display@14f1e000mediatek,mt8195-mdp3-color?v q +display@14f1f000mediatek,mt8195-mdp3-ovl?w q + display@14f20000mediatek,mt8195-mdp3-padding? q +display@14f21000mediatek,mt8195-mdp3-padding? q +display@14f22000mediatek,mt8195-mdp3-padding?  q +dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot?0 q 0  + dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot?@ q @  + dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot?P q P  r+ clock-controller@15000000mediatek,mt8195-imgsys?$larb@15001000mediatek,mt8195-smi-larb? %  $$$  apbsmigals+smi@15002000mediatek,mt8195-smi-sub-common? $$apbsmigals0 s+smi@15003000mediatek,mt8195-smi-sub-common?0$$$ apbsmigals0 +clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top?larb@15120000mediatek,mt8195-smi-larb? %  $apbsmi+clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr?clock-controller@15220000mediatek,mt8195-imgsys1_wpe?"larb@15230000mediatek,mt8195-smi-larb?# %  $apbsmi+clock-controller@15330000mediatek,mt8195-ipesys?3%larb@15340000mediatek,mt8195-smi-larb?4 %  %%apbsmi+zclock-controller@16000000mediatek,mt8195-camsys?&larb@16001000mediatek,mt8195-smi-larb? %  &&& apbsmigals+larb@16002000mediatek,mt8195-smi-larb?  % &&apbsmi+{smi@16004000mediatek,mt8195-smi-sub-common?@&&&apbsmigals0 +smi@16005000mediatek,mt8195-smi-sub-common?P&&apbsmigals0 s+larb@16012000mediatek,mt8195-smi-larb?  % apbsmi+ |larb@16013000mediatek,mt8195-smi-larb?0 % apbsmi+ larb@16014000mediatek,mt8195-smi-larb?@ % apbsmi+!larb@16015000mediatek,mt8195-smi-larb?P % apbsmi+!clock-controller@1604f000mediatek,mt8195-camsys_rawa?clock-controller@1606f000mediatek,mt8195-camsys_yuva?clock-controller@1608f000mediatek,mt8195-camsys_rawb?clock-controller@160af000mediatek,mt8195-camsys_yuvb? clock-controller@16140000mediatek,mt8195-camsys_mraw?larb@16141000mediatek,mt8195-smi-larb? % && apbsmigals+"larb@16142000mediatek,mt8195-smi-larb?  % apbsmi+"clock-controller@17200000mediatek,mt8195-ccusys? larb@17201000mediatek,mt8195-smi-larb?  % apbsmi+}video-codec@18000000mediatek,mt8195-vcodec-dec E + ?@Y`video-codec@2000mediatek,mtk-vcodec-lat-soc?  rr A  selvdeclattopA+video-codec@10000mediatek,mtk-vcodec-lat?0  A  selvdeclattopA+video-codec@25000mediatek,mtk-vcodec-core?PP  AselvdeclattopA+larb@1800d000mediatek,mt8195-smi-larb? %  apbsmi+larb@1800e000mediatek,mt8195-smi-larb? %  apbsmi+clock-controller@1800f000mediatek,mt8195-vdecsys_soc? larb@1802e000mediatek,mt8195-smi-larb? % apbsmi+clock-controller@1802f000mediatek,mt8195-vdecsys?larb@1803e000mediatek,mt8195-smi-larb? % !apbsmi+clock-controller@1803f000mediatek,mt8195-vdecsys_core1?!clock-controller@190f3000mediatek,mt8195-apusys_pll?0clock-controller@1a000000mediatek,mt8195-vencsys?"larb@1a010000mediatek,mt8195-smi-larb? % ""apbsmi+video-codec@1a020000mediatek,mt8195-vcodec-enc?H `abcdvwxyU E" venc_sel@++jpgdec-mastermediatek,mt8195-jpgdec+0 mnrstu+Yjpgdec@1a040000mediatek,mt8195-jpgdec-hw?0 mnrstuW"jpgdec+jpgdec@1a050000mediatek,mt8195-jpgdec-hw?0 mnrstuX"jpgdec+jpgdec@1b040000mediatek,mt8195-jpgdec-hw?0 rrrrrr\jpgdec+clock-controller@1b000000mediatek,mt8195-vencsys_core1?syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon?  jpgenc-mastermediatek,mt8195-jpgenc+ rrrr+Yjpgenc@1a030000mediatek,mt8195-jpgenc-hw? ghilV"jpgenc+jpgenc@1b030000mediatek,mt8195-jpgenc-hw? rrrr[jpgenc+larb@1b010000mediatek,mt8195-smi-larb? % s  apbsmigals+~ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl?|+  rdma@1c002000mediatek,mt8195-disp-rdma? ~+   color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color?0+ 0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr?@+ @aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal?P+ Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma?`+ `dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither?p+  pdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi?+*enginedigitalhs- dphy disableddsc@1c009000mediatek,mt8195-disp-dsc?+ dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi? ++enginedigitalhs- dphy disabledmerge@1c014000mediatek,mt8195-disp-merge?@+ @dp-intf@1c015000mediatek,mt8195-dp-intf?P,enginepixelpll disabledmutex@1c016000mediatek,mt8195-disp-mutex?`+ ` Ularb@1c018000mediatek,mt8195-smi-larb? % ((  apbsmigals+larb@1c019000mediatek,mt8195-smi-larb? % s(  apbsmigals+usyscon@1c100000mediatek,mt8195-vdosys1syscon?  #smi@1c01b000mediatek,mt8195-smi-common-vdo? %&)$apbsmigals0gals1+iommu@1c01f000mediatek,mt8195-iommu-vdo?8 6'bclk+mutex@1c101000mediatek,mt8195-disp-mutex? vdo1_mutex+# vdo1_mutex  larb@1c102000mediatek,mt8195-smi-larb?  % ### apbsmigals+larb@1c103000mediatek,mt8195-smi-larb?0 % s##  apbsmigals+vdma-controller@1c104000mediatek,mt8195-vdo1-rdma?@#+ @ @ dma-controller@1c105000mediatek,mt8195-vdo1-rdma?P#+ r` P dma-controller@1c106000mediatek,mt8195-vdo1-rdma?`#+ A ` dma-controller@1c107000mediatek,mt8195-vdo1-rdma?p#+ ra p dma-controller@1c108000mediatek,mt8195-vdo1-rdma?#+ B  dma-controller@1c109000mediatek,mt8195-vdo1-rdma?#+ rb  dma-controller@1c10a000mediatek,mt8195-vdo1-rdma?#+ C  dma-controller@1c10b000mediatek,mt8195-vdo1-rdma?#+ rc  vpp-merge@1c10c000mediatek,mt8195-disp-merge?# #mergemerge_async+  R#vpp-merge@1c10d000mediatek,mt8195-disp-merge?# #mergemerge_async+  R#vpp-merge@1c10e000mediatek,mt8195-disp-merge?# #mergemerge_async+  R#vpp-merge@1c10f000mediatek,mt8195-disp-merge?# #mergemerge_async+  R#vpp-merge@1c110000mediatek,mt8195-disp-merge?# #mergemerge_async+  f#dp-intf@1c113000mediatek,mt8195-dp-intf?0+##/enginepixelpll disabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp?@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pph#%# ###!#$#"#1#&#'#(#)#*mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top+ rdre(#3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx?P:Fdp_calibration_data+ } disableddp-tx@1c600000mediatek,mt8195-dp-tx?`:Fdp_calibration_data+ } disabledthermal-zonescpu0-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu2-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu3-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu4-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu5-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu6-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu7-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 vpu0-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalvpu1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalgpu-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalgpu1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalvdec-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalimg-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalinfra-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcam0-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcam1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalchosen serial0:921600n8firmwareopteelinaro,optee-tzJsmcmemory@400000003memory?@regulator-wifi-3v3-enregulator-fixed wifi_3v3_enN2Z2Z  UCdefault Kregulator-vsysregulator-fixedvsysN LK@LK@ Kregulator-vsys-buckregulator-fixed vsys_buckN LK@LK@ Xregulator-vcc5v0-sysregulator-fixed vcc5v0_sysN reserved-memory+Yoptee@43200000?C  )memory@50000000shared-dma-pool?P ))memory@53000000shared-dma-pool?S@memory@54600000?T`  )memory@60000000shared-dma-pool?` )memory@62000000shared-dma-pool?b@ compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typedp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4ethernet0serial0serial1spi0spi1device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxdrive-strengthinput-enableoutput-highbias-disableinput-disablebias-pull-updrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsmemory-regionpower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-0pinctrl-names#io-channel-cellsnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,tx-delay-psmediatek,mac-wolsnps,reset-gpiosnps,reset-delays-ussnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeuprole-switch-default-modeusb-role-switchvusb33-supplyvbus-supplyremote-endpointbus-widthmax-frequencyhs400-ds-delaycap-mmc-highspeedcap-mmc-hw-resetmmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN1-supplyLDO_VIN3-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolesource-pdossink-pdosmode-switchorientation-switchvcc-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,scpmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathenable-active-highvin-supplyregulator-boot-onno-map