+j8t( <Uedgeble,neural-compute-module-6a-ioedgeble,neural-compute-module-6arockchip,rk3588 +7Edgeble Neu6A IO Boardaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci+ 2 B0,W gt@@  cpu@100cpuarm,cortex-a55 psci+ W gt@@ cpu@200cpuarm,cortex-a55 psci+ W gt@@ cpu@300cpuarm,cortex-a55 psci+ W gt@@ cpu@400cpuarm,cortex-a76 psci+ 2 B0,W gt@@cpu@500cpuarm,cortex-a76 psci+ W gt@@cpu@600cpuarm,cortex-a76 psci+ 2 B0,W gt@@cpu@700cpuarm,cortex-a76 psci+ W gt@@ idle-states pscicpu-sleeparm,idle-state*AdRxb l2-cache-l0cacheiv@s l2-cache-l1cacheiv@sl2-cache-l2cacheiv@sl2-cache-l3cacheiv@sl2-cache-b0cacheiv@sl2-cache-b1cacheiv@sl2-cache-b2cacheiv@sl2-cache-b3cacheiv@sl3-cachecachei0v@sdisplay-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemgpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf 2 B +corecoregroupstacks 0\]^ jobmmugpu#  1disabledopp-tableoperating-points-v2opp-3000000008 ? L L Popp-4000000008ׄ ? L L Popp-5000000008e ? L L Popp-6000000008#F ? L L Popp-7000000008)' ? ` ` Popp-8000000008/ ? q q Popp-90000000085 ? 5 5 Popp-10000000008; ? P P Pusb@fc000000rockchip,rk3588-dwc3snps,dwc3@+ref_clksuspend_clkbus_clkMotg U Zusb2-phyusb3-phy dutmi_wide#mRt 1disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci+!U"Zusb#1okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci+!U"Zusb#1okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci+#U$Zusb#1okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci+#U$Zusb#1okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(+jihkr&ref_clksuspend_clkbus_clkutmipipeMhostU% Zusb3-phy dutmi_widem4t 1okayiommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-sync: 1disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-sync: 1disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXesyscon@fd58c000rockchip,rk3588-sys-grfsysconX`syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ asyscon@fd5a6000rockchip,rk3588-vo-grfsysconZ` +syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ+bsyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@syscon@fd5b0000rockchip,rk3588-php-grfsyscon[(syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@0rockchip,rk3588-usb2phy+phyclk usb480m_phy0mmGphyapb 1disabledotg-portS 1disabledsyscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy+phyclk usb480m_phy2moGphyapb1okay!host-portS1okay^&"syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy+phyclk usb480m_phy3mp Gphyapb1okay#host-portS1okay^'$syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|2]q@BA.2Fq)׫ׄe/ׄ eZ р i(i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=+ts i2cpclkv)default+1okayregulator@42rockchip,rk8602Bvdd_cpu_big0_s0dp%&regulator-state-mem0regulator@43 rockchip,rk8603rockchip,rk8602Cvdd_cpu_big1_s0dp%&regulator-state-mem0serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK+baudclkapb_pclkI**Ntxrxv+defaultXb 1disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclkv,defaulto 1disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclkv-defaulto 1disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm + pwmpclkv.defaulto1okaypwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ pwmpclkv/defaulto 1disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdcpower-controller!rockchip,rk3588-power-controllerz+1okaypower-domain@8z+power-domain@9  +!#" 012z+power-domain@10 +!#"3zpower-domain@11 +!#"4zpower-domain@12 +5678zpower-domain@13 +zpower-domain@14(+9zpower-domain@15 +:zpower-domain@16+ ;<=+zpower-domain@17 + >?@zpower-domain@21+ ABCDEFGH+zpower-domain@23+CAIzpower-domain@14 +9zpower-domain@15+:zpower-domain@22+Jzpower-domain@24+[Z]KL+zpower-domain@258+ZMzpower-domain@268+QNOzpower-domain@270+PQRS+zpower-domain@28 +TUzpower-domain@29(+VWzpower-domain@30+z{Xzpower-domain@31@+WYZ[\zpower-domain@33!+WZ[zpower-domain@34"+WZ[zpower-domain@37%+2]zpower-domain@38&+45zpower-domain@40(^zvideo-codec@fdc70000rockchip,rk3588-av1-vpulvdpu2ACBׄׄ+AC aclkhclk# mvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8+]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop_#i`abc 1disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~+]\ aclkiface:# 1disabled_i2s@fddc0000rockchip,rk3588-i2s-tdm+mclk_txmclk_rxhclk2IdNtx#mGtx-m 1disabledi2s@fddf0000rockchip,rk3588-i2s-tdm+445mclk_txmclk_rxhclk21IdNtx#mGtx-m 1disabledi2s@fddfc000rockchip,rk3588-i2s-tdm+00,mclk_txmclk_rxhclk2-IdNrx#mGrx-m 1disabledqos@fdf35000rockchip,rk3588-qossysconP 5qos@fdf35200rockchip,rk3588-qossysconR 6qos@fdf35400rockchip,rk3588-qossysconT 7qos@fdf35600rockchip,rk3588-qossysconV 8qos@fdf36000rockchip,rk3588-qossyscon` Xqos@fdf39000rockchip,rk3588-qossyscon ]qos@fdf3d800rockchip,rk3588-qossyscon ^qos@fdf3e000rockchip,rk3588-qossyscon Zqos@fdf3e200rockchip,rk3588-qossyscon Yqos@fdf3e400rockchip,rk3588-qossyscon [qos@fdf3e600rockchip,rk3588-qossyscon \qos@fdf40000rockchip,rk3588-qossyscon Vqos@fdf40200rockchip,rk3588-qossyscon Wqos@fdf40400rockchip,rk3588-qossyscon Pqos@fdf40500rockchip,rk3588-qossyscon Qqos@fdf40600rockchip,rk3588-qossyscon Rqos@fdf40800rockchip,rk3588-qossyscon Sqos@fdf41000rockchip,rk3588-qossyscon Tqos@fdf41100rockchip,rk3588-qossyscon Uqos@fdf60000rockchip,rk3588-qossyscon ;qos@fdf60200rockchip,rk3588-qossyscon <qos@fdf60400rockchip,rk3588-qossyscon =qos@fdf61000rockchip,rk3588-qossyscon >qos@fdf61200rockchip,rk3588-qossyscon ?qos@fdf61400rockchip,rk3588-qossyscon @qos@fdf62000rockchip,rk3588-qossyscon 9qos@fdf63000rockchip,rk3588-qossyscon0 :qos@fdf64000rockchip,rk3588-qossyscon@ Iqos@fdf66000rockchip,rk3588-qossyscon` Aqos@fdf66200rockchip,rk3588-qossysconb Bqos@fdf66400rockchip,rk3588-qossyscond Cqos@fdf66600rockchip,rk3588-qossysconf Dqos@fdf66800rockchip,rk3588-qossysconh Eqos@fdf66a00rockchip,rk3588-qossysconj Fqos@fdf66c00rockchip,rk3588-qossysconl Gqos@fdf66e00rockchip,rk3588-qossysconn Hqos@fdf67000rockchip,rk3588-qossysconp Jqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 3qos@fdf71000rockchip,rk3588-qossyscon 4qos@fdf72000rockchip,rk3588-qossyscon 0qos@fdf72200rockchip,rk3588-qossyscon" 1qos@fdf72400rockchip,rk3588-qossyscon$ 2qos@fdf80000rockchip,rk3588-qossyscon Mqos@fdf81000rockchip,rk3588-qossyscon Nqos@fdf81200rockchip,rk3588-qossyscon Oqos@fdf82000rockchip,rk3588-qossyscon Kqos@fdf82200rockchip,rk3588-qossyscon" Ldfi@fe060000rockchip,rk3588-dfi@&0:epcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0+CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`+ffff9JY0g0aU% Zpcie-phy#"T @ @0 @@dbiapbconfigm). Gpwrpipe+ 1disabledlegacy-interrupt-controllerk fpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0+DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`+hhhh9JY@g@aUi Zpcie-phy#"T @ @0 A@dbiapbconfigm*/ Gpwrpipe+ 1disabledlegacy-interrupt-controllerk hethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref#!m$ Gstmmacethi`(jkl 1disabledmdiosnps,dwmac-mdio+stmmac-axi-configjrx-queues-config kqueue0queue1tx-queues-config!lqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(+b_eTosatapmaliverxoobrefasic7+1okaysata-port@0I@Ui Zsata-phyV e sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(+dagVqsatapmaliverxoobrefasic7+ 1disabledsata-port@0I@U% Zsata-phyV e spi@fe2b0000 rockchip,sfc+@+/0clk_sfchclk_sfc+ 1disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ +  biuciuciu-driveciu-samplet defaultvmnop#(1okayqrmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ +biuciuciu-driveciu-samplet defaultvs#% 1disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.2-., B n6 (+,*+-.corebusaxiblocktimer vtuvwxdefault(mGcorebusaxiblocktimer1okayi2s@fe470000rockchip,rk3588-i2s-tdmG++/(mclk_txmclk_rxhclk2)-I**Ntxrx#&m*+ Gtx-mrx-m8default(vyz{|}~ 1disabledi2s@fe480000rockchip,rk3588-i2s-tdmH+y}umclk_txmclk_rxhclkI**Ntxrxm^_ Gtx-mrx-m8default(v 1disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI+i2s_clki2s_hclk2INtxrx#&defaultv 1disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ+%i2s_clki2s_hclk2"INtxrx#&defaultv 1disabledinterrupt-controller@fe600000 arm,gic-v3 `h kSa]8h+msi-controller@fe640000arm,gic-v3-itsdhwgmsi-controller@fe660000arm,gic-v3-itsfhwppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW+n apb_pclk*dma-controller@fea30000arm,pl330arm,primecell@ XY+o apb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c+{ i2cpclk>vdefault+ 1disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c+| i2cpclk?vdefault+ 1disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c+} i2cpclk@vdefault+ 1disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c+~ i2cpclkAvdefault+ 1disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkBvdefault+ 1disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !+TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt+dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF+spiclkapb_pclkI**Ntxrx vdefault+ 1disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG+spiclkapb_pclkI**Ntxrx vdefault+ 1disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH+spiclkapb_pclkINtxrxvdefault+1okay2B pmic@0rockchip,rk806B@ defaultv&&& & & & && 2& >& J& W d& q ~ &  dvs1-null-pins gpio_pwrctrl1 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1 vdd_gpu_s0dp~0 regulator-state-mem0dcdc-reg2vdd_cpu_lit_s0dp~0 regulator-state-mem0dcdc-reg3 vdd_log_s0 L q0regulator-state-mem0 qdcdc-reg4 vdd_vdenc_s0dp~0regulator-state-mem0dcdc-reg5 vdd_ddr_s0 L 0regulator-state-mem0 Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg7vdd_2v0_pldo_s30regulator-state-mem  dcdc-reg8 vcc_3v3_s32Z2Zqregulator-state-mem  2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem0dcdc-reg10 vcc_1v8_s3w@w@regulator-state-mem  w@pldo-reg1 avcc_1v8_s0w@w@regulator-state-mem0pldo-reg2 vcc_1v8_s0w@w@regulator-state-mem0 w@pldo-reg3 avdd_1v2_s0OOregulator-state-mem0pldo-reg4 vcc_3v3_s02Z2Z0regulator-state-mem0pldo-reg5 vccio_sd_s0w@2Z0rregulator-state-mem0pldo-reg6 pldo6_s3w@w@regulator-state-mem  w@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem  qnldo-reg2vdd_ddr_pll_s0 P Pregulator-state-mem0 Pnldo-reg3 avdd_0v75_s0 q qregulator-state-mem0nldo-reg4 vdd_0v85_s0 P Pregulator-state-mem0nldo-reg5 vdd_0v75_s0 q qregulator-state-mem0spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI+spiclkapb_pclkINtxrx vdefault+ 1disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL+baudclkapb_pclkI** NtxrxvdefaultbX 1disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM+baudclkapb_pclkI* * NtxrxvdefaultbX1okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN+baudclkapb_pclkI* * NtxrxvdefaultbX 1disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO+baudclkapb_pclkI NtxrxvdefaultbX 1disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP+baudclkapb_pclkI NtxrxvdefaultbX 1disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ+baudclkapb_pclkI NtxrxvdefaultbX1okayserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR+baudclkapb_pclkIddNtxrxvdefaultbX1okayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS+baudclkapb_pclkId d NtxrxvdefaultbX 1disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT+baudclkapb_pclkId d NtxrxvdefaultbX 1disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkvdefaulto 1disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkvdefaulto 1disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +LK pwmpclkvdefaulto 1disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+LK pwmpclkvdefaulto 1disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkvdefaulto 1disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkvdefaulto 1disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +ON pwmpclkvdefaulto 1disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ON pwmpclkvdefaulto 1disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkvdefaulto 1disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkvdefaulto 1disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +RQ pwmpclkvdefaulto 1disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+RQ pwmpclkvdefaulto 1disabledtsadc@fec00000rockchip,rk3588-tsadc+tsadcapb_pclk2BmVWGtsadc-apbtsadc  ( ?v Z gpiootpout d 1disabledadc@fec10000rockchip,rk3588-saradc z+saradcapb_pclkmU Gsaradc-apb 1disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkCvdefault+1okayrtc@51haoyu,hym8563Q hym8563defaultv i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkDvdefault+ 1disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkEvdefault+ 1disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ+spiclkapb_pclkId dNtxrx vdefault+ 1disabledefuse@fecc0000rockchip,rk3588-otp +otpapb_pclkphyarbm Gotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[+p apb_pclkdphy@fed60000rockchip,rk3588-hdptx-phy +TrefapbS8m#cde!""Gphyapbinitcmnlaneroplllcplli 1disabledphy@fed80000rockchip,rk3588-usbdp-phyS+lVrefclkimmortalpclkutmi(m   Ginitcmnlanepcs_apbpma_apb     1disabled phy@fee00000rockchip,rk3588-naneng-combphy+vW refapbpipe2BSm<CGphyapb ( 1okayiphy@fee20000rockchip,rk3588-naneng-combphy+xW refapbpipe2BSm>EGphyapb ( 1okay%sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrli+gpio@fd8a0000rockchip,gpio-bank+qr   k gpio@fec20000rockchip,gpio-bank+st   k gpio@fec30000rockchip,gpio-bank+uv  @ k gpio@fec40000rockchip,gpio-bank+wx  ` k gpio@fec50000rockchip,gpio-bank+yz   k pcfg-pull-up pcfg-pull-down *pcfg-pull-none 9pcfg-pull-none-drv-level-2 9 Fpcfg-pull-up-drv-level-1  Fpcfg-pull-up-drv-level-2  Fpcfg-pull-none-smt 9 Uauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout jtemmc-bus8 juemmc-clk jvemmc-cmd jwemmc-data-strobe jxeth1fspigmac1gpuhdmii2c0i2c0m2-xfer j)i2c1i2c1m0-xfer j  i2c2i2c2m0-xfer j  i2c3i2c3m0-xfer j  i2c4i2c4m0-xfer j  i2c5i2c5m0-xfer j  i2c6i2c6m0-xfer j  i2c7i2c7m0-xfer j  i2c8i2c8m0-xfer j  i2s0i2s0-lrck jyi2s0-sclk jzi2s0-sdi0 j{i2s0-sdi1 j|i2s0-sdi2 j}i2s0-sdi3 j~i2s0-sdo0 ji2s0-sdo1 ji2s0-sdo2 ji2s0-sdo3 ji2s1i2s1m0-lrck ji2s1m0-sclk ji2s1m0-sdi0 ji2s1m0-sdi1 ji2s1m0-sdi2 ji2s1m0-sdi3 ji2s1m0-sdo0 j i2s1m0-sdo1 j i2s1m0-sdo2 j i2s1m0-sdo3 j i2s2i2s2m1-lrck ji2s2m1-sclk j i2s2m1-sdi j i2s2m1-sdo j i2s3i2s3-lrck ji2s3-sclk ji2s3-sdi ji2s3-sdo jjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp jpmupwm0pwm0m0-pins j,pwm1pwm1m0-pins j-pwm2pwm2m1-pins j .pwm3pwm3m0-pins j/pwm4pwm4m0-pins j pwm5pwm5m0-pins j pwm6pwm6m0-pins j pwm7pwm7m0-pins j pwm8pwm8m0-pins j pwm9pwm9m0-pins j pwm10pwm10m0-pins j pwm11pwm11m0-pins j pwm12pwm12m0-pins j pwm13pwm13m0-pins j pwm14pwm14m0-pins j pwm15pwm15m0-pins j refclksatasata0sata1sata2sdiosdiom1-pins` jssdmmcsdmmc-bus4@ jpsdmmc-clk jmsdmmc-cmd jnsdmmc-det jospdif0spdif1spi0spi0m0-pins0 jspi0m0-cs0 jspi0m0-cs1 jspi1spi1m1-pins0 jspi1m1-cs0 jspi1m1-cs1 jspi2spi2m2-pins0 j spi2m2-cs0 j spi3spi3m1-pins0 j spi3m1-cs0 jspi3m1-cs1 jspi4spi4m0-pins0 jspi4m0-cs0 jspi4m0-cs1 jtsadctsadc-shut juart0uart0m1-xfer j +uart1uart1m1-xfer j  uart2uart2m0-xfer j uart3uart3m1-xfer j  uart4uart4m1-xfer j  uart5uart5m1-xfer j  uart6uart6m0-xfer j  uart7uart7m2-xfer j  uart8uart8m1-xfer j  uart9uart9m1-xfer j  vopbt656gpio-functsadc-gpio-func jeth0gmac0ledsled_user_en jpcie2pcie2-0-rst jpcie3pcie3x2-rst jpcie3x2-vcc3v3-en jpcie3x4-rst jpcie3x4-vcc3v3-en jhym8563hym8563-int jusbvcc5v0-host-en jusb@fc400000rockchip,rk3588-dwc3snps,dwc3@@+ref_clksuspend_clkbus_clkMotg UZusb2-phyusb3-phy dutmi_wide#mSt 1disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+usb2phy@4000rockchip,rk3588-usb2phy@+phyclk usb480m_phy1mnGphyapb 1disabledotg-portS 1disabledi2s@fddc8000rockchip,rk3588-i2s-tdm܀+mclk_txmclk_rxhclk2IdNtx#mGtx-m 1disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@+99?mclk_txmclk_rxhclk26IdNtx#mGtx-m 1disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀+++'mclk_txmclk_rxhclk2(IdNrx#mGrx-m 1disabledi2s@fde00000rockchip,rk3588-i2s-tdm+&&"mclk_txmclk_rxhclk2#IdNrx#mGrx-m 1disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`+9JYaU Zpcie-phy#"T @ @0 @@dbiapbconfigm&+ Gpwrpipe1okaydefaultv x legacy-interrupt-controllerk pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`+9JYaU Zpcie-phy#"T @ @@0 @@@dbiapbconfigm', Gpwrpipe1okaydefaultv x legacy-interrupt-controllerk pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0+BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`+9JY g aU Zpcie-phy#"T @ @0 @@dbiapbconfigm(- Gpwrpipe+1okaydefaultv x legacy-interrupt-controllerk ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref#!m# Gstmmacethi`( 1disabledmdiosnps,dwmac-mdio+stmmac-axi-configrx-queues-config queue0queue1tx-queues-config!queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(+c`fUpsatapmaliverxoobrefasic7+ 1disabledsata-port@0I@U Zsata-phyV e phy@fed90000rockchip,rk3588-usbdp-phyS+mWrefclkimmortalpclkutmi(mGinitcmnlanepcs_apbpma_apb     1disabledphy@fee10000rockchip,rk3588-naneng-combphy+wW refapbpipe2BSm=DGphyapb ( 1okayphy@fee80000rockchip,rk3588-pcie3-phyS+ypclkmHGphy ( 1okaygpio-leds gpio-ledsled-0  heartbeat ~ heartbeatdefaultvvcc12v-dcin-regulatorregulator-fixed vcc12v_dcinvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@%&vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3%&chosen serial2:1500000n8vcc3v3-pcie2x1l0-regulatorregulator-fixedvcc3v3_pcie2x1l02Z2Z %qvcc3v3-pcie3x2-regulatorregulator-fixed  ~defaultvvcc3v3_pcie3x22Z2Z %&vcc3v3-pcie3x4-regulatorregulator-fixed  ~defaultvvcc3v3_pcie3x42Z2Z %&vcc5v0-host-regulatorregulator-fixed  defaultv vcc5v0_hostLK@LK@%&' compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namesoperating-points-v2power-domainsstatusopp-hzopp-microvoltdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyrockchip,phy-grfcolorlinux,default-triggerstdout-pathstartup-delay-usenable-active-highgpio