78)|( )D&friendlyarm,nanopc-t6rockchip,rk3588 +7FriendlyElec NanoPC-T6aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000/mmc@fe2c0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci0 7 G0,\ ly@@   cpu@100cpuarm,cortex-a55 psci0 \ ly@@  cpu@200cpuarm,cortex-a55 psci0 \ ly@@  cpu@300cpuarm,cortex-a55 psci0 \ ly@@  cpu@400cpuarm,cortex-a76 psci0 7 G0,\ ly@@ cpu@500cpuarm,cortex-a76 psci0 \ ly@@ cpu@600cpuarm,cortex-a76 psci0 7 G0,\ ly@@ cpu@700cpuarm,cortex-a76 psci0 \ ly@@ idle-statespscicpu-sleeparm,idle-state/FdWxg l2-cache-l0cachen{@x l2-cache-l1cachen{@x l2-cache-l2cachen{@x l2-cache-l3cachen{@x l2-cache-b0cachen{@x l2-cache-b1cachen{@x l2-cache-b2cachen{@x l2-cache-b3cachen{@x l3-cachecachen0{@x display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14  protocol@16 pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram +sram@0arm,scmi-shmem  gpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf 7 G 0corecoregroupstacks 0\]^ jobmmugpu(  6disabledopp-tableoperating-points-v2 opp-300000000= D L L Popp-400000000=ׄ D L L Popp-500000000=e D L L Popp-600000000=#F D L L Popp-700000000=)' D ` ` Popp-800000000=/ D q q Popp-900000000=5 D 5 5 Popp-1000000000=; D P P Pusb@fc000000rockchip,rk3588-dwc3snps,dwc3 @0ref_clksuspend_clkbus_clkRotg Z _usb2-phyusb3-phy iutmi_wide(rRy 6disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci 0!Z"_usb(6okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci 0!Z"_usb(6okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci 0#Z$_usb(6okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci 0#Z$_usb(6okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3 @(0jihkr&ref_clksuspend_clkbus_clkutmipipeRhostZ% _usb3-phy iutmi_wider4y% 6disablediommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-sync? 6disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-sync? 6disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfd X esyscon@fd58c000rockchip,rk3588-sys-grfsyscon X `syscon@fd5a4000rockchip,rk3588-vop-grfsyscon Z@  asyscon@fd5a6000rockchip,rk3588-vo-grfsyscon Z` 0 syscon@fd5a8000rockchip,rk3588-vo-grfsyscon Z0 bsyscon@fd5ac000rockchip,rk3588-usb-grfsyscon Z@ syscon@fd5b0000rockchip,rk3588-php-grfsyscon [ 'syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon [ syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon \@ syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon \@ syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+ usb2phy@0rockchip,rk3588-usb2phy 0phyclk usb480m_phy0rmLphyapb 6disabled otg-portX 6disabled syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2phy@8000rockchip,rk3588-usb2phy 0phyclk usb480m_phy2roLphyapb6okay !host-portX6okayc& "syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@+usb2phy@c000rockchip,rk3588-usb2phy 0phyclk usb480m_phy3rp Lphyapb6okay #host-portX6okay $syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon ^ syscon@fd5f0000rockchip,rk3588-iocsyscon _ sram@fd600000 mmio-sram ``+clock-controller@fd7c0000rockchip,rk3588-cru |7]q@GA.2Fq)׫ׄe/ׄ eZ р n' i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c =0ts i2cpclk{(default+6okayregulator@42rockchip,rk8602 Bvdd_cpu_big0_s0dp*) regulator-state-mem5regulator@43 rockchip,rk8603rockchip,rk8602 Cvdd_cpu_big1_s0dp*) regulator-state-mem5serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uart K0baudclkapb_pclkN**Stxrx{+default]g 6disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 pwmpclk{,defaultt 6disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 pwmpclk{-defaultt6okaypwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0 pwmpclk{.defaultt 6disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00 pwmpclk{/defaultt 6disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd  cpower-controller!rockchip,rk3588-power-controller+6okay power-domain@8 +power-domain@9  0!#" 012+power-domain@10 0!#"3power-domain@11 0!#"4power-domain@12 05678power-domain@13 +power-domain@14 (09power-domain@15  0:power-domain@16 0 ;<=+power-domain@17  0 >?@power-domain@21 0 ABCDEFGH+power-domain@23 0CAIpower-domain@14  09power-domain@15 0:power-domain@22 0Jpower-domain@24 0[Z]KL+power-domain@25 80ZMpower-domain@26 80QNOpower-domain@27 00PQRS+power-domain@28  0TUpower-domain@29 (0VWpower-domain@30 0z{Xpower-domain@31 @0WYZ[\power-domain@33 !0WZ[power-domain@34 "0WZ[power-domain@37 %02]power-domain@38 &045power-domain@40 (^video-codec@fdc70000rockchip,rk3588-av1-vpu lvdpu7ACGׄׄ0AC aclkhclk( rvop@fdd90000rockchip,rk3588-vop  BPvopgamma-lut80]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop_(n`abc 6disabledports+ port@0+ port@1+ port@2+ port@3+ iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu  ~0]\ aclkiface?( 6disabled _i2s@fddc0000rockchip,rk3588-i2s-tdm 0mclk_txmclk_rxhclk7NdStx(rLtx-m 6disabledi2s@fddf0000rockchip,rk3588-i2s-tdm 0445mclk_txmclk_rxhclk71NdStx(rLtx-m 6disabledi2s@fddfc000rockchip,rk3588-i2s-tdm 000,mclk_txmclk_rxhclk7-NdSrx(rLrx-m 6disabledqos@fdf35000rockchip,rk3588-qossyscon P  5qos@fdf35200rockchip,rk3588-qossyscon R  6qos@fdf35400rockchip,rk3588-qossyscon T  7qos@fdf35600rockchip,rk3588-qossyscon V  8qos@fdf36000rockchip,rk3588-qossyscon `  Xqos@fdf39000rockchip,rk3588-qossyscon  ]qos@fdf3d800rockchip,rk3588-qossyscon  ^qos@fdf3e000rockchip,rk3588-qossyscon  Zqos@fdf3e200rockchip,rk3588-qossyscon  Yqos@fdf3e400rockchip,rk3588-qossyscon  [qos@fdf3e600rockchip,rk3588-qossyscon  \qos@fdf40000rockchip,rk3588-qossyscon  Vqos@fdf40200rockchip,rk3588-qossyscon   Wqos@fdf40400rockchip,rk3588-qossyscon   Pqos@fdf40500rockchip,rk3588-qossyscon   Qqos@fdf40600rockchip,rk3588-qossyscon   Rqos@fdf40800rockchip,rk3588-qossyscon   Sqos@fdf41000rockchip,rk3588-qossyscon   Tqos@fdf41100rockchip,rk3588-qossyscon   Uqos@fdf60000rockchip,rk3588-qossyscon  ;qos@fdf60200rockchip,rk3588-qossyscon   <qos@fdf60400rockchip,rk3588-qossyscon   =qos@fdf61000rockchip,rk3588-qossyscon   >qos@fdf61200rockchip,rk3588-qossyscon   ?qos@fdf61400rockchip,rk3588-qossyscon   @qos@fdf62000rockchip,rk3588-qossyscon  9qos@fdf63000rockchip,rk3588-qossyscon 0  :qos@fdf64000rockchip,rk3588-qossyscon @  Iqos@fdf66000rockchip,rk3588-qossyscon `  Aqos@fdf66200rockchip,rk3588-qossyscon b  Bqos@fdf66400rockchip,rk3588-qossyscon d  Cqos@fdf66600rockchip,rk3588-qossyscon f  Dqos@fdf66800rockchip,rk3588-qossyscon h  Eqos@fdf66a00rockchip,rk3588-qossyscon j  Fqos@fdf66c00rockchip,rk3588-qossyscon l  Gqos@fdf66e00rockchip,rk3588-qossyscon n  Hqos@fdf67000rockchip,rk3588-qossyscon p  Jqos@fdf67200rockchip,rk3588-qossyscon r qos@fdf70000rockchip,rk3588-qossyscon  3qos@fdf71000rockchip,rk3588-qossyscon   4qos@fdf72000rockchip,rk3588-qossyscon  0qos@fdf72200rockchip,rk3588-qossyscon "  1qos@fdf72400rockchip,rk3588-qossyscon $  2qos@fdf80000rockchip,rk3588-qossyscon  Mqos@fdf81000rockchip,rk3588-qossyscon   Nqos@fdf81200rockchip,rk3588-qossyscon   Oqos@fdf82000rockchip,rk3588-qossyscon  Kqos@fdf82200rockchip,rk3588-qossyscon "  Ldfi@fe060000 rockchip,rk3588-dfi@&0:epcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?00CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `0ffff>O^0g0fZ% _pcie-phy("T @ @0 @@dbiapbconfigr). Lpwrpipe+6okay ph|idefault{jlegacy-interrupt-controller   fpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O00DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `0kkkk>O^@g@fZl _pcie-phy("T @ @0 A@dbiapbconfigr*/ Lpwrpipe+6okay ph|mdefault{nlegacy-interrupt-controller   kethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a  macirqeth_wake_irq(067Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref(!r$ Lstmmacethn`'opq 6disabledmdiosnps,dwmac-mdio+stmmac-axi-config  orx-queues-config, pqueue0queue1tx-queues-configB qqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci !(0b_eTosatapmaliverxoobrefasicX+ 6disabledsata-port@0 j@Zl _sata-phyw  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci #(0dagVqsatapmaliverxoobrefasicX+ 6disabledsata-port@0 j@Z% _sata-phyw  spi@fe2b0000 rockchip,sfc +@0/0clk_sfchclk_sfc+ 6disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc ,@ 0  biuciuciu-driveciu-sample default{rstu((6okay v wxmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc -@ 0biuciuciu-driveciu-sample default{y(% 6disabledmmc@fe2e0000rockchip,rk3588-dwcmshc .7-., G n6 (0,*+-.corebusaxiblocktimer {z{|}~default(rLcorebusaxiblocktimer6okay%+9Hi2s@fe470000rockchip,rk3588-i2s-tdm G0+/(mclk_txmclk_rxhclk7)-N**Stxrx(&r*+ Ltx-mrx-mbdefault{6okay portendpoint}i2s i2s@fe480000rockchip,rk3588-i2s-tdm H0y}umclk_txmclk_rxhclkN**Stxrxr^_ Ltx-mrx-mbdefault({ 6disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2s I0i2s_clki2s_hclk7NStxrx(&default{ 6disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2s J0%i2s_clki2s_hclk7"NStxrx(&default{ 6disabledinterrupt-controller@fe600000 arm,gic-v3  `h a8 + msi-controller@fe640000arm,gic-v3-its d gmsi-controller@fe660000arm,gic-v3-its f ppi-partitionsinterrupt-partition-0 interrupt-partition-1  dma-controller@fea10000arm,pl330arm,primecell @ VW0n apb_pclk *dma-controller@fea30000arm,pl330arm,primecell @ XY0o apb_pclk i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c 0{ i2cpclk>{default+ 6disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0| i2cpclk?{default+6okayregulator@42rockchip,rk8602 B vdd_npu_s0dp~*)regulator-state-mem5i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0} i2cpclk@{default+ 6disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0~ i2cpclkA{default+ 6disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 i2cpclkB{default+ 6disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !0TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt 0dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spi F0spiclkapb_pclkN**Stxrx  {default+ 6disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spi G0spiclkapb_pclkN**Stxrx  {default+ 6disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spi H0spiclkapb_pclkNStxrx {default+6okay7G pmic@0rockchip,rk806 #B@  vdefault{ 5 M) Y) e) q) }) ) ) ) ) )  )   )  dvs1-null-pins "gpio_pwrctrl1 'pin_fun0 dvs2-null-pins "gpio_pwrctrl2 'pin_fun0 dvs3-null-pins "gpio_pwrctrl3 'pin_fun0 regulatorsdcdc-reg1dp~0 vdd_gpu_s0 0regulator-state-mem5dcdc-reg2dp~0vdd_cpu_lit_s0 regulator-state-mem5dcdc-reg3 L q0 vdd_log_s0regulator-state-mem5 L qdcdc-reg4dp~ h q0 vdd_vdenc_s0regulator-state-mem5dcdc-reg5 L 0 vdd_ddr_s0regulator-state-mem5 L Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg70vdd_2v0_pldo_s3 regulator-state-mem  Ldcdc-reg82Z2Z vcc_3v3_s3 regulator-state-mem  L2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem5dcdc-reg10w@w@ vcc_1v8_s3regulator-state-mem  Lw@pldo-reg1w@w@ avcc_1v8_s0 regulator-state-mem5pldo-reg2w@w@ vcc_1v8_s0regulator-state-mem5 Lw@pldo-reg3OO avdd_1v2_s0regulator-state-mem5pldo-reg42Z2Z0 vcc_3v3_s0regulator-state-mem5pldo-reg5w@2Z0 vccio_sd_s0 xregulator-state-mem5pldo-reg6w@w@ pldo6_s3regulator-state-mem  Lw@nldo-reg1 q q vdd_0v75_s3regulator-state-mem  L qnldo-reg2 P Pvdd_ddr_pll_s0regulator-state-mem5 L Pnldo-reg3 q q avdd_0v75_s0regulator-state-mem5nldo-reg4 P P vdd_0v85_s0regulator-state-mem5nldo-reg5 q q vdd_0v75_s0regulator-state-mem5spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spi I0spiclkapb_pclkNStxrx  {default+ 6disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uart L0baudclkapb_pclkN** Stxrx{defaultg] 6disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uart M0baudclkapb_pclkN* * Stxrx{defaultg]6okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uart N0baudclkapb_pclkN* * Stxrx{defaultg] 6disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uart O0baudclkapb_pclkN Stxrx{defaultg] 6disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uart P0baudclkapb_pclkN Stxrx{defaultg] 6disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uart Q0baudclkapb_pclkN Stxrx{defaultg] 6disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uart R0baudclkapb_pclkNddStxrx{defaultg] 6disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uart S0baudclkapb_pclkNd d Stxrx{defaultg] 6disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uart T0baudclkapb_pclkNd d Stxrx{defaultg] 6disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK pwmpclk{defaultt 6disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK pwmpclk{defaultt 6disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0LK pwmpclk{defaultt 6disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00LK pwmpclk{defaultt 6disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON pwmpclk{defaultt 6disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON pwmpclk{defaultt 6disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0ON pwmpclk{defaultt 6disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00ON pwmpclk{defaultt 6disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ pwmpclk{defaultt 6disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ pwmpclk{defaultt 6disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 0RQ pwmpclk{defaultt 6disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm 00RQ pwmpclk{defaultt 6disabledtsadc@fec00000rockchip,rk3588-tsadc 0tsadcapb_pclk7GrVWLtsadc-apbtsadc   {  gpiootpout 6okayadc@fec10000rockchip,rk3588-saradc  0saradcapb_pclkrU Lsaradc-apb6okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c 0 i2cpclkC{default+6okay @typec-portc@22 fcs,fusb302 " v{default connectorusb-c-connector ,dual 6USB-C ELphyapb ' 6okay %sram@ff001000 mmio-sram +pinctrlrockchip,rk3588-pinctrln+ gpio@fd8a0000rockchip,gpio-bank 0qr     ; HEADER_10HEADER_08HEADER_32 vgpio@fec20000rockchip,gpio-bank 0st      HEADER_27HEADER_28HEADER_15HEADER_26HEADER_21HEADER_19HEADER_23HEADER_24HEADER_22HEADER_05HEADER_03 gpio@fec30000rockchip,gpio-bank 0uv  @   . CSI1_11CSI1_12 gpio@fec40000rockchip,gpio-bank 0wx  `    HEADER_35HEADER_38HEADER_40HEADER_36HEADER_37DSI0_12HEADER_33DSI0_10HEADER_07HEADER_16HEADER_18HEADER_29HEADER_31HEADER_12DSI0_08DSI0_14HEADER_11HEADER_13DSI1_10gpio@fec50000rockchip,gpio-bank 0yz     C DSI1_08DSI1_14DSI1_12CSI0_11CSI0_12 hpcfg-pull-up  pcfg-pull-down , pcfg-pull-none ; pcfg-pull-none-drv-level-2 ; H pcfg-pull-up-drv-level-1  H pcfg-pull-up-drv-level-2  H pcfg-pull-none-smt ; W auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout l zemmc-bus8 l {emmc-clk l |emmc-cmd l }emmc-data-strobe l ~eth1fspigmac1gpuhdmii2c0i2c0m2-xfer l (i2c1i2c1m0-xfer l   i2c2i2c2m0-xfer l   i2c3i2c3m0-xfer l   i2c4i2c4m0-xfer l   i2c5i2c5m0-xfer l   i2c6i2c6m0-xfer l   i2c7i2c7m0-xfer l   i2c8i2c8m2-xfer l   i2s0i2s0-lrck l i2s0-mclk l i2s0-sclk l i2s0-sdi0 l i2s0-sdo0 l i2s1i2s1m0-lrck l i2s1m0-sclk l i2s1m0-sdi0 l i2s1m0-sdi1 l i2s1m0-sdi2 l i2s1m0-sdi3 l i2s1m0-sdo0 l  i2s1m0-sdo1 l  i2s1m0-sdo2 l  i2s1m0-sdo3 l  i2s2i2s2m1-lrck l i2s2m1-sclk l  i2s2m1-sdi l  i2s2m1-sdo l  i2s3i2s3-lrck l i2s3-sclk l i2s3-sdi l i2s3-sdo l jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp l pmupwm0pwm0m0-pins l ,pwm1pwm1m1-pins l  -pwm2pwm2m0-pins l .pwm3pwm3m0-pins l /pwm4pwm4m0-pins l  pwm5pwm5m0-pins l  pwm6pwm6m0-pins l  pwm7pwm7m0-pins l  pwm8pwm8m0-pins l  pwm9pwm9m0-pins l  pwm10pwm10m0-pins l  pwm11pwm11m0-pins l  pwm12pwm12m0-pins l  pwm13pwm13m0-pins l  pwm14pwm14m0-pins l  pwm15pwm15m0-pins l  refclksatasata0sata1sata2sdiosdiom1-pins` l ysdmmcsdmmc-bus4@ l usdmmc-clk l rsdmmc-cmd l ssdmmc-det l tspdif0spdif1spi0spi0m0-pins0 l spi0m0-cs0 l spi0m0-cs1 l spi1spi1m1-pins0 l spi1m1-cs0 l spi1m1-cs1 l spi2spi2m2-pins0 l  spi2m2-cs0 l  spi3spi3m1-pins0 l  spi3m1-cs0 l spi3m1-cs1 l spi4spi4m0-pins0 l spi4m0-cs0 l spi4m0-cs1 l tsadctsadc-shut l uart0uart0m1-xfer l  +uart1uart1m1-xfer l   uart2uart2m0-xfer l  uart3uart3m1-xfer l   uart4uart4m1-xfer l   uart5uart5m1-xfer l   uart6uart6m1-xfer l   uart7uart7m1-xfer l   uart8uart8m1-xfer l   uart9uart9m1-xfer l   vopbt656gpio-functsadc-gpio-func l eth0gmac0gpio-ledssys-led-pin l usr-led-pin l headphonehp-det l hym8563hym8563-int l pciepcie2-0-rst l  pcie2-1-rst l jpcie2-2-rst l npcie-m20-pwren l pcie-m21-pwren l usb4g-lte-pwren l typec5v-pwren l usbc0-int l usb@fc400000rockchip,rk3588-dwc3snps,dwc3 @@0ref_clksuspend_clkbus_clkRotg Z_usb2-phyusb3-phy iutmi_wide(rSy 6disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon [ syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon \ syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon \@ syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ]@@+ usb2phy@4000rockchip,rk3588-usb2phy @0phyclk usb480m_phy1rnLphyapb 6disabled otg-portX 6disabled i2s@fddc8000rockchip,rk3588-i2s-tdm ܀0mclk_txmclk_rxhclk7NdStx(rLtx-m 6disabledi2s@fddf4000rockchip,rk3588-i2s-tdm @099?mclk_txmclk_rxhclk76NdStx(rLtx-m 6disabledi2s@fddf8000rockchip,rk3588-i2s-tdm ߀0++'mclk_txmclk_rxhclk7(NdSrx(rLrx-m 6disabledi2s@fde00000rockchip,rk3588-i2s-tdm 0&&"mclk_txmclk_rxhclk7#NdSrx(rLrx-m 6disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+00@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `0>O^fZ _pcie-phy("T @ @0 @@dbiapbconfigr&+ Lpwrpipe6okay ph|legacy-interrupt-controller   pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+00AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `0>O^fZ _pcie-phy("T @ @@0 @@@dbiapbconfigr', Lpwrpipe 6disabledlegacy-interrupt-controller   pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /00BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `0>O^ g fZ _pcie-phy("T @ @0 @@dbiapbconfigr(- Lpwrpipe+6okay ph |mdefault{legacy-interrupt-controller   ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a  macirqeth_wake_irq(067X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref(!r# Lstmmacethn`' 6disabledmdiosnps,dwmac-mdio+stmmac-axi-config  rx-queues-config, queue0queue1tx-queues-configB queue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci "(0c`fUpsatapmaliverxoobrefasicX+ 6disabledsata-port@0 j@Z _sata-phyw  phy@fed90000rockchip,rk3588-usbdp-phy X0mWrefclkimmortalpclkutmi(rLinitcmnlanepcs_apbpma_apb     6disabled phy@fee10000rockchip,rk3588-naneng-combphy 0wW refapbpipe7GXr=DLphyapb ' 6okay phy@fee80000rockchip,rk3588-pcie3-phy X0ypclkrHLphy ' z6okay chosen serial2:1500000n8leds gpio-ledsled-0 v 6system-led heartbeatdefault{led-1 v 6user-leddefault{soundsimple-audio-carddefault{ realtek,rt5616-codec i2s   Headphones0 3HeadphoneHeadphonesMicrophoneMicrophone JackN MHeadphonesHPOLHeadphonesHPORMIC1Microphone JackMicrophone Jackmicbias1simple-audio-card,cpu gsimple-audio-card,codec gvcc12v-dcin-regulatorregulator-fixed vcc12v_dcin vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@* vcc4v0-sys-regulatorregulator-fixed vcc4v0_sys= = * )vcc-1v1-nldo-s3-regulatorregulator-fixedvcc-1v1-nldo-s3*) vcc3v3-pcie20-regulatorregulator-fixedvcc_3v3_pcie202Z2Z* mvbus5v0-typec-regulatorregulator-fixed q default{vbus5v0_typecLK@LK@* vcc3v3-pcie2x1l0-regulatorregulator-fixed q hdefault{vcc3v3_pcie2x1l02Z2Z* ivcc3v3-pcie30-regulatorregulator-fixed q vdefault{vcc3v3_pcie302Z2Z* vcc3v3-sd-s0-regulatorregulator-fixed  h2Z2Z vcc3v3_sd_s0* wvdd-4g-3v3-regulatorregulator-fixed q hdefault{ vdd_4g_3v32Z2Z* & compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namesoperating-points-v2power-domainsstatusopp-hzopp-microvoltdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsrockchip,suspend-voltage-selectornum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-init-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyvbus-supplydata-rolelabelpower-roletry-power-rolesource-pdossink-pdosop-sink-microwattwakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathlinux,default-triggersimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,hp-det-gpiosimple-audio-card,hp-pin-namesimple-audio-card,widgetssimple-audio-card,routingsound-daienable-active-highenable-active-low